A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applicationsTAKEDA, Koichi; HAGIHARA, Yasuhiko; AIMOTO, Yoshiharu et al.IEEE journal of solid-state circuits. 2006, Vol 41, Num 1, pp 113-121, issn 0018-9200, 9 p.Conference Paper

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMsTAKEDA, Koichi; SAITO, Toshio; ASAYAMA, Shinobu et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 4, pp 806-814, issn 0018-9200, 9 p.Conference Paper

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modesNOMURA, Masahiro; IKENAGA, Yoshifumi; TAKEDA, Koichi et al.IEEE journal of solid-state circuits. 2006, Vol 41, Num 4, pp 805-814, issn 0018-9200, 10 p.Conference Paper